1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device having a high voltage (HV) device and a low voltage (LV) device on a silicon on insulator (SOI) substrate and a method of making the same.
2. Background of the Related Art
A background art substrate having a thick epitaxial layer can implement a high voltage (HV) breakdown. Because a device can operate at a relatively high voltage by forming a relatively large depletion region with a deep junction depth, an HV device can be formed in the substrate by forming a deep well in the epitaxial layer, using a long drive-in process.
Because diffusion must occur at a temperature of about 1200xc2x0 C. for at least about 1000 minutes when forming the background art deep well, processing time is unavoidably lengthened and throughput is reduced. Further, since a junction isolation or a self-isolation process is required to isolate an HV trench region (TR) from a low voltage (LV) TR, a chip size must be large, thus causing difficulty in integrating the isolation process with a normal CMOS process.
To address the above-described background art problems, a background art power integrated circuit (IC) technique using a silicon on insulator (SOI) substrate is employed. A SOI power IC does not require a deep junction, and the power IC technique can reduce the chip size by implementing a trench isolation between HV and LV devices. Further, the power IC technique considerably improves a fabrication throughput, and enables integration with the normal CMOS process.
FIGS. 1A through 1D illustrate cross-sectional views of a background art semiconductor device isolation method. FIG. 1A shows a buried insulating layer 3 formed on a semiconductor substrate 1, and a P-type single crystal silicon layer 5 formed on the buried insulating layer 3 by silicon epitaxy, at a thickness of about 500-2000 xc3x85. Next, a pad oxide film 7 is formed on the single crystal silicon layer 5 by thermal oxidation, and a mask layer 9 is formed on the pad oxide film 7 by chemical vapor deposition (CVD) of silicon nitrite.
FIG. 1B shows the mask layer 9 and the pad oxide film 7 being patterned by a photo-etching method to expose the single crystal silicon layer 5. An HV region, an LV region and a field region are accordingly formed, where the field region electrically insulates the HV region from the LV region.
Next, an anisotropic etching process, such as a reactive ion etching method (RIE), is used to form a trench 11 in the single crystal silicon layer 5, using the mask layer 9 as an etching mask. The trench 11 exposes the buried insulating layer 3.
FIG. 1C shows the substrate of FIG. 1B with the mask layer 9 and the pad oxide film 7 removed to expose a surface of the single crystal silicon layer 5. A silicon oxide layer 13 is deposited by CVD on the crystal silicon layer 5 to fill the trench 11. Then, as shown in FIG. 1D, an etchback process, such as RIE or chemical mechanical polishing (CMP), is applied to the silicon oxide layer 13 to expose the single crystal silicon layer 5. As a result, a field oxide film 13 is formed in the trench 11, and the background art semiconductor device isolation method is completed and followed by fabrication of a background art integrated circuit.
FIG. 2 illustrates a cross-sectional diagram of a semiconductor device fabricated on the substrate shown in FIG. 1D. N-type drift regions 15 are formed in the single crystal silicon layer 5 of the HV and LV regions by a single process, and a P-well region 17 is formed adjacent to the N-type drift region 15 of the HV region. Further, gate electrodes 19 having a gate oxide film (not shown)are formed on the single crystal silicon layer 5 in the HV and LV regions, and N-type impurity regions are formed as source S and drain D regions in the single crystal silicon layer 5 at both sides of each gate electrode 19.
An N-type body contact region 21 is formed adjacent to the source region S of the HV region, and a metal field plate electrode 23 is formed on the single crystal layer 5 on the drift region 15 of the HV region. The drain region D of the HV region is separated from the gate electrode 19 of the drift region 15, and the metal field plate electrode 23 is insulated from the single crystal layer 15 and the gate electrode 19.
The background art has various problems and disadvantages. In the background art semiconductor device isolation method, the HV and LV regions are isolated from each other by the trench 11 and the buried insulating layer 3. Thus, conduction of heat generated during the operation of the device is blocked, and a heat accumulation problem results. Additionally, the trench process is complicated by a dielectric isolation (DI) requirement, and the manufacturing cost of the semiconductor device is increased by the required use of an expensive SOI substrate.
An object of the present invention is to obviate at least one or more of the problems and disadvantages in the background art and to provide at least the following advantages.
Another object of the invention is to reduce the cost and/or complexity of the fabricating process.
Another object of the present invention is to obviate the problem of heat generation.
It is also an object of the present invention to achieve a simple fabricating process that does not require the lengthy and complex drive-in and trench processes.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a semiconductor device isolation structure, which includes a semiconductor substrate having first and second trenches, a first insulating film formed on the first and second trenches, first conductive type regions formed on the first insulating film to fill in the first and second trenches, and a second insulating film formed on parts of the semiconductor substrate corresponding to the first and second trenches.
Also, to achieve the objects of the present invention, there is provided a semiconductor device isolation method, which comprises the steps of forming first and second trenches on a semiconductor substrate; forming a first insulating film on the first and second trenches; forming first conductive type patterns on the first insulating film to fill in the first and second trenches; and forming a second insulating film by oxidizing a part of the semiconductor substrate between the first and second trenches.
An alternative semiconductor device isolation method embodying the present invention includes the steps of: forming a pad oxide film on the semiconductor substrate; forming a mask layer on the pad oxide film; partially exposing an upper surface of the semiconductor substrate by removing parts of the pad oxide film and the mask layer corresponding to first and second trench regions; forming first and second trenches by applying an anisotropic etching process to the semiconductor substrate using the mask layer as an etching mask; forming a first insulating film in the first and second trenches; forming first conductive type single crystal patterns in the first and second trenches, respectively, such that a portion of the semiconductor substrate remains exposed; and forming a second insulating film by oxidizing the exposed portion of the semiconductor substrate.
A semiconductor device embodying the present invention includes a semiconductor substrate having first and second trenches; a first insulating film formed on the first and second trenches; first conductive type single crystal silicon patterns formed on the first insulating film to fill in the first and second trenches, respectively; a second insulating film formed on a part of the semiconductor substrate between the first and second trenches; a second conductive type drift region formed in the first conductive type single crystal silicon patterns of the first and second trenches; a first conductive type well region formed in the single crystal silicon pattern in the first trench; gate electrodes formed on the single crystal silicon patterns in the first and second trenches by forming a gate insulating film therein; second conductive type impurity regions formed in the single crystal silicon patterns at both sides of each gate electrode, the second conductive type impurity regions being used as a source or a drain; a first conductive type body contact region formed in the first conductive type well region of an HV region; and a metal field plate electrode formed on the single crystal silicon layer in the first trench.
A fabrication method of a semiconductor device embodying the present invention includes forming a pad oxide film on a semiconductor substrate; forming a mask layer on the pad oxide film; removing parts of the pad oxide film and the mask layer corresponding to first and second trench regions; forming first and second trenches by etching the semiconductor substrate using the mask layer as an etching mask; forming a first insulating film in the first and second trenches; forming a first conductive type single crystal silicon pattern over the semiconductor substrate including the buried insulating film to fill in the trenches; partially removing the first conductive type single crystal silicon pattern by an etching process to expose a part of a top surface of the semiconductor substrate between the first and second trenches; forming a second insulating film by oxidizing the exposed part of the semiconductor substrate; forming a second conductive type drift region in single crystal silicon patterns formed in the first and second trenches, respectively; forming a first conductive type well region in the first trench; forming gate electrodes on predetermined regions of the single crystal silicon patterns formed in the first and second trenches, the gate electrodes having a gate insulating film therein; forming impurity regions in the single crystal silicon patterns at both sides of the gate electrodes, the impurity regions being used as source or drain; forming a first conductive type body contact region in a well region of an HV region; and forming a metal field plate electrode on a part of the single crystal silicon pattern corresponding to the drift region in the first trench.
An alternative semiconductor device embodying the present invention includes a substrate comprising a semiconductor material; a first conductive region on a first portion of the substrate; a second conductive region on a second portion of the substrate; and an intermediate insulating region comprising a third portion of the substrate, said intermediate insulating region separating the first and second conductive regions.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.